SAROSH_
An EDA-automation engineer pivoting into DFT, with the silicon-adjacent background most DFT candidates lack: 1.5 years building EDA / layout-automation tooling, plus ASIC physical-design training (floorplanning, placement, CTS, STA), now aimed squarely at design-for-test.
I design test circuitry and the automation that verifies it: scan chains, ATPG, fault modeling; Python, TCL, Bash to eliminate the manual steps. At Elbrus Labs (1.5 yrs) I built Python/GDSPY layout-automation tools: a node-migration tool that ports standard cells and metal layers down a technology node, a latchup-detection tool, and Tkinter/PyGTK GUIs that standardised the team's flow. Essentially EDA tool design.
Now focused on DFT: a scan-chain simulator, a stuck-at fault simulator at 100% coverage on its test set, a synthesizable Verilog scan chain with a self-checking testbench. I understand why a chip must be testable, and I build the code that makes it repeatable.
My core is the automation & EDA tooling a DFT flow runs on (1.5y industry). DFT methods are my active focus: self-study and projects, not yet industry-tenured. Bars are honest self-assessment, not a score.
Scan-chain simulator (shift/capture/shift-out), stuck-at fault simulator at 100% coverage on its test set, and a synthesizable Verilog scan chain with a self-checking testbench.
Parses Liberty (.lib) standard-cell files for timing/power, auto-generates HTML reports and emails them from the terminal. EDA-flow automation in Bash.
A team-built working 8-bit CPU from 60+ discrete 74LS ICs + EEPROM microcode (SAP-1). Breadboard to PCB. Silicon from the gate up.
Python CLI (v3.0) scoring 270+ equities across 27 sectors on fundamentals: rich terminal UI, CSV export, systemd timer.
A UPS-backed Raspberry Pi self-hosting 18+ Docker services behind Cloudflare Tunnel and Authelia SSO, recursive DNS, 3-tier backups.
My Arch + Hyprland workstation as code: one install script, systemd units, helper scripts. The environment I do all this in.
| Rev | Date | Role & description |
|---|---|---|
| C | Oct 2021 – Jan 2023 | Trainee Engineer - EDA & Layout Automation · Elbrus Labs
|
| B | Jun – Jul 2019 | Embedded Systems Intern · Tantech Solutions
|
| A | Jun – Jul 2018 | VLSI & Digital Design Intern · Aujus Technology
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| Year | Program | Focus |
|---|---|---|
| 2026 | Self-Directed DFT Study
Scan insertion, ATPG, fault modeling, JTAG/BIST: hands-on Python & Verilog. Formal certification (VLSI Guru / Maven Silicon) planned. | |
| 2019–20 | ASIC Physical Design · PinE Training Academy
Floorplanning, placement, CTS, routing, STA; Bash/TCL/Python for PD automation. | |
| Jun–Jul 2018 | Digital Design, Verilog & Schematics · PinE Training Academy
RTL flip-flops, MUX/DMUX, adders, dividers; schematic entry; Xilinx ISE / Vivado. | |
| 2016–20 | B.Tech, Electronics & Communication · Inderprastha Engineering College (AKTU)
E-Yantra Robotics (Technical Head) · NCC 'B' Certificate (Alpha grade). |
Technical Head of E-Yantra Robotics: ran a hands-on robotics & embedded-systems workshop series (Arduino/8051, electronic components, C, Proteus) for 30+ junior students. 3× National Gymnastics Medallist (SGFI). Volunteer at Bhartiya Janhit Kalyan Samiti (NGO) since 2014. I lead end-to-end event planning, management and execution with a team I build, plus annual food-distribution and education drives.
Best reached by email, or find me on GitHub / LinkedIn. Bengaluru-based, fully remote-ready.